EP3SE50F484I4L vs EP3SE50F484I4LG Comparación
Comparación detallada lado a lado de EP3SE50F484I4L por Intel y EP3SE50F484I4LG por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP3SE50F484I4L - Stratix III E FPGA, 47.5K LE, 484-FBGA | Intel
EP3SE50F484I4L ⚠ Última compraIntel
EP3SE50F484I4LG - 47.5K LE Stratix III E FPGA, 484-FCBGA | Intel
EP3SE50F484I4LG ⚠ Última compraComparación de especificaciones
| Parámetro | EP3SE50F484I4L | EP3SE50F484I4LG |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1.290,00 | $1.340,00 |
| Family | Stratix III E | Stratix III (Enhanced) |
| Logic Elements (LE) | 47,500 | 47,500 |
| Logic Array Blocks (LABs) | 1,900 | — |
| Adaptive Logic Modules (ALMs) | [DATA_NEEDED: ALM count] | 19,000 |
| Embedded Memory | 5,760 Kbit (5.625 Mbit) | — |
| Embedded Multipliers (18x18) | 384 | — |
| Maximum User I/O | 296 | — |
| Maximum Core Clock | 717 MHz (per third-party listing) | — |
| Speed Grade | 4 (slowest) | — |
| Rango de temperatura de funcionamiento | Industrial (I): -40C to +100C junction | -40C to +100C (Industrial, TJ) |
| Process Node | 40 nm CMOS | — |
| Encapsulado | 484-ball FCBGA (FBGA-484) | 484-ball FBGA / FCBGA |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount (SMD/SMT) |
| Tensión de alimentación | Multiple rails: core 0.9V, I/O 1.2V-3.3V (per Stratix III handbook) | — |
| Configuration Method | Quartus II / EPCS serial / parallel | — |
| Lead-Free (Pb-free) | Yes (L suffix) | — |
| Estado RoHS | Compliant | Compliant |
| Nivel MSL | MSL3 (per JEDEC J-STD-020, typical for FBGA-484) | — |
| Series | — | Stratix III E |
| LABs/CLBs | — | 1,900 |
| Total Embedded Memory | — | 5,760,000 bits (5.49 Mbit / 5.76 Mbit per source) |
| Number of DSP Blocks | — | 104 (18x18 multipliers) |
| Number of PLLs | — | 8 |
| User I/O Count | — | 296 |
| Core Supply Voltage (Vccint) | — | 0.86 V to 1.15 V (1.1 V nominal) |
| Packaging | — | Tray |
| Process Technology | — | 40 nm CMOS |
| Configuration Interface | — | Passive Serial / Fast Passive Parallel / JTAG |
| Bitstream Encryption | — | 256-bit AES |