EP3SE50F484I4L vs EP3SE50F484I4LG Comparaison
Comparaison détaillée côte à côte de EP3SE50F484I4L par Intel et EP3SE50F484I4LG par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP3SE50F484I4L - Stratix III E FPGA, 47.5K LE, 484-FBGA | Intel
EP3SE50F484I4L ⚠ Dernier achatIntel
EP3SE50F484I4LG - 47.5K LE Stratix III E FPGA, 484-FCBGA | Intel
EP3SE50F484I4LG ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP3SE50F484I4L | EP3SE50F484I4LG |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 290,00 | $1 340,00 |
| Family | Stratix III E | Stratix III (Enhanced) |
| Logic Elements (LE) | 47,500 | 47,500 |
| Logic Array Blocks (LABs) | 1,900 | — |
| Adaptive Logic Modules (ALMs) | [DATA_NEEDED: ALM count] | 19,000 |
| Embedded Memory | 5,760 Kbit (5.625 Mbit) | — |
| Embedded Multipliers (18x18) | 384 | — |
| Maximum User I/O | 296 | — |
| Maximum Core Clock | 717 MHz (per third-party listing) | — |
| Speed Grade | 4 (slowest) | — |
| Plage de température de fonctionnement | Industrial (I): -40C to +100C junction | -40C to +100C (Industrial, TJ) |
| Process Node | 40 nm CMOS | — |
| Boîtier | 484-ball FCBGA (FBGA-484) | 484-ball FBGA / FCBGA |
| Type de montage | Surface Mount (BGA) | Surface Mount (SMD/SMT) |
| Tension d'alimentation | Multiple rails: core 0.9V, I/O 1.2V-3.3V (per Stratix III handbook) | — |
| Configuration Method | Quartus II / EPCS serial / parallel | — |
| Lead-Free (Pb-free) | Yes (L suffix) | — |
| Statut RoHS | Compliant | Compliant |
| Niveau MSL | MSL3 (per JEDEC J-STD-020, typical for FBGA-484) | — |
| Series | — | Stratix III E |
| LABs/CLBs | — | 1,900 |
| Total Embedded Memory | — | 5,760,000 bits (5.49 Mbit / 5.76 Mbit per source) |
| Number of DSP Blocks | — | 104 (18x18 multipliers) |
| Number of PLLs | — | 8 |
| User I/O Count | — | 296 |
| Core Supply Voltage (Vccint) | — | 0.86 V to 1.15 V (1.1 V nominal) |
| Packaging | — | Tray |
| Process Technology | — | 40 nm CMOS |
| Configuration Interface | — | Passive Serial / Fast Passive Parallel / JTAG |
| Bitstream Encryption | — | 256-bit AES |