EP3SL50F484C3 vs EP3SL50F484C2G Comparación
Comparación detallada lado a lado de EP3SL50F484C3 por Intel y EP3SL50F484C2G por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP3SL50F484C3 | EP3SL50F484C2G |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $335,00 |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Family | Stratix III L | Stratix III L |
| Logic Cells | 47,500 cells | — |
| Technology | 65 nm | — |
| Listed Frequency | 500 MHz | — |
| Internal Frequency | 800 MHz | — |
| Tensión de alimentación | 1.1 V | — |
| Logic Array Blocks | 1,900 LABs | — |
| User I/O | 296 I/Os | — |
| Encapsulado | 484-pin FC-FBGA | 484-ball FCBGA (FBGA-484) |
| Recuento de pines | 484 pins | — |
| Package Type | FBGA-484 | — |
| Temperatura de funcionamiento | 0 °C to 85 °C | — |
| Device Category | Programmable logic IC | — |
| Tipo de montaje | Surface Mount | — |
| Manufacturer Technology Description | 65-nm low-power high-performance FPGA | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Halogen-Free Status | [DATA_NEEDED: halogen-free status] | — |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| Configuration Memory | [DATA_NEEDED: configuration memory size] | — |
| Embedded Transceivers | [DATA_NEEDED: embedded transceiver count] | — |
| Power Consumption | [DATA_NEEDED: power consumption] | — |
| Logic Elements | — | 47,500 LE |
| Adaptive Logic Modules (ALMs) | — | 19,000 ALM |
| Embedded Memory | — | 2,184,192 bits (2.08 Mbit) |
| Maximum User I/Os | — | 296 I/O |
| Number of LABs/CLBs | — | [DATA_NEEDED: LAB count] |
| Operating Supply Voltage (Core) | — | 1.1 V |
| Maximum Operating Temperature | — | +85 C |
| Minimum Operating Temperature | — | 0 C |
| Frecuencia de reloj máxima | — | 600 MHz |
| Process Technology | — | 65 nm CMOS |
| Estilo de montaje | — | SMD/SMT |
| Packaging | — | Tray |
| Total Transceivers | — | [DATA_NEEDED: transceiver count] |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |