EP610DC-15 vs EP610DC-30 Comparación
Comparación detallada lado a lado de EP610DC-15 por Altera y EP610DC-30 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP610DC-15 | EP610DC-30 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,95 | $10,40 |
| Product Family | Classic EPLD (EP610) | — |
| Architecture | UV-erasable CMOS PAL-type | — |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 | 4 (4 product terms per macrocell) |
| Dedicated Inputs | 20 | 16 |
| Bidirectional I/O Pins | 16 | — |
| Total Product Terms | 160 | — |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | 30 ns |
| Maximum Internal Clock Frequency | 71.4 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Temperatura de funcionamiento | 0C to 70C (commercial) | Commercial (0C to +70C) |
| Encapsulado | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin CERDIP (windowed) |
| Tipo de montaje | Through-Hole | Through-Hole |
| Programming Method | JEDEC fuse map, UV erasure | — |
| Technology | CMOS | CMOS EPROM |
| Estado RoHS | [DATA_NEEDED: RoHS status] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP610 (Classic Device Family) |
| Usable Gates | — | 300 |
| Maximum Pipelined Clock Frequency | — | 100 MHz |
| I/O Pins | — | 16 (with output enable) |
| Speed Grade | — | -30 (30 ns tPD) |
| Programmability | — | UV-erasable, windowed EPROM |
| Security Bit | — | Yes (protects design after programming) |
| Output Modes | — | Registered and Combinatorial |