EP610DC-15 vs EP610DC-30 比較
詳細な並列比較: EP610DC-15 メーカー: Altera および EP610DC-30 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP610DC-15 | EP610DC-30 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $7.95 | $10.40 |
| Product Family | Classic EPLD (EP610) | — |
| Architecture | UV-erasable CMOS PAL-type | — |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 | 4 (4 product terms per macrocell) |
| Dedicated Inputs | 20 | 16 |
| Bidirectional I/O Pins | 16 | — |
| Total Product Terms | 160 | — |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | 30 ns |
| Maximum Internal Clock Frequency | 71.4 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| 動作温度 | 0C to 70C (commercial) | Commercial (0C to +70C) |
| パッケージ | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin CERDIP (windowed) |
| 実装タイプ | Through-Hole | Through-Hole |
| Programming Method | JEDEC fuse map, UV erasure | — |
| Technology | CMOS | CMOS EPROM |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP610 (Classic Device Family) |
| Usable Gates | — | 300 |
| Maximum Pipelined Clock Frequency | — | 100 MHz |
| I/O Pins | — | 16 (with output enable) |
| Speed Grade | — | -30 (30 ns tPD) |
| Programmability | — | UV-erasable, windowed EPROM |
| Security Bit | — | Yes (protects design after programming) |
| Output Modes | — | Registered and Combinatorial |