EP610DC-30 vs EP610ILC-10 Comparación
Comparación detallada lado a lado de EP610DC-30 por Altera y EP610ILC-10 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP610DC-30 | EP610ILC-10 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,40 | $7,20 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | UV-Erasable / OTP PLD |
| Family | EP610 (Classic Device Family) | — |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 (4 product terms per macrocell) | — |
| Usable Gates | 300 | 300 |
| Maximum Pipelined Clock Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 30 ns | — |
| Dedicated Inputs | 16 | 4 |
| I/O Pins | 16 (with output enable) | 16 |
| Encapsulado | 24-pin CERDIP (windowed) | PLCC-28 (plastic J-lead chip carrier) |
| Tipo de montaje | Through-Hole | Surface Mount (PLCC socket or solder) |
| Speed Grade | -30 (30 ns tPD) | — |
| Technology | CMOS EPROM | — |
| Programmability | UV-erasable, windowed EPROM | — |
| Security Bit | Yes (protects design after programming) | — |
| Output Modes | Registered and Combinatorial | — |
| Temperatura de funcionamiento | Commercial (0C to +70C) | [DATA_NEEDED: operating temperature range] |
| Device Family | — | Classic EPLD |
| Architecture | — | PAL-type with macrocells |
| Product Terms | — | 160 |
| Tensión de alimentación | — | 5 V (single supply) |
| Pin-to-Pin Delay (tPD) | — | 10 ns (grade -10) |
| Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family Compatibility | — | TTL (5 V CMOS/TTL-compatible I/O) |
| Estado RoHS | — | [DATA_NEEDED: RoHS compliance] |