EP610DC-30 vs EP610ILC-10 Comparaison
Comparaison détaillée côte à côte de EP610DC-30 par Altera et EP610ILC-10 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP610DC-30 | EP610ILC-10 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $10,40 | $7,20 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | UV-Erasable / OTP PLD |
| Family | EP610 (Classic Device Family) | — |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 (4 product terms per macrocell) | — |
| Usable Gates | 300 | 300 |
| Maximum Pipelined Clock Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 30 ns | — |
| Dedicated Inputs | 16 | 4 |
| I/O Pins | 16 (with output enable) | 16 |
| Boîtier | 24-pin CERDIP (windowed) | PLCC-28 (plastic J-lead chip carrier) |
| Type de montage | Through-Hole | Surface Mount (PLCC socket or solder) |
| Speed Grade | -30 (30 ns tPD) | — |
| Technology | CMOS EPROM | — |
| Programmability | UV-erasable, windowed EPROM | — |
| Security Bit | Yes (protects design after programming) | — |
| Output Modes | Registered and Combinatorial | — |
| Température de fonctionnement | Commercial (0C to +70C) | [DATA_NEEDED: operating temperature range] |
| Device Family | — | Classic EPLD |
| Architecture | — | PAL-type with macrocells |
| Product Terms | — | 160 |
| Tension d'alimentation | — | 5 V (single supply) |
| Pin-to-Pin Delay (tPD) | — | 10 ns (grade -10) |
| Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family Compatibility | — | TTL (5 V CMOS/TTL-compatible I/O) |
| Statut RoHS | — | [DATA_NEEDED: RoHS compliance] |