EP610DI-25 vs EP610DI-30N Comparación
Comparación detallada lado a lado de EP610DI-25 por Intel y EP610DI-30N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP610DI-25 | EP610DI-30N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $17,80 |
| Part Family | Classic EPLD | — |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 25 ns | 30 ns |
| Maximum Pipelined Clock Frequency | 100 MHz (max fCNT, per family datasheet) | — |
| I/O Pins | 16 (bidirectional) | — |
| Dedicated Inputs | 4 | — |
| Total User I/O | 20 | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Supply Voltage (VCC) | 5 V nominal | 5 V ±5% |
| Package Type | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 | — |
| Recuento de pines | 24 | 24 |
| Tipo de montaje | Through-Hole (DIP) | Through-hole (DIP) |
| Temperatura de funcionamiento | Industrial (per "I" suffix) | -40°C to +85°C (industrial) |
| Speed Grade Suffix | 25 = 25 ns | — |
| Compliance | RoHS status unknown (legacy 1990s part) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic EP610 |
| Usable Gates | — | 300 |
| Maximum Frequency | — | 33.3 MHz (system); 100 MHz (pipelined) |
| Encapsulado | — | CDIP-24 (Ceramic DIP, windowed) |
| Process Technology | — | CMOS |
| Programming Method | — | UV-erasable (windowed ceramic) |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |
| Estado RoHS | — | [DATA_NEEDED: RoHS status] |