EP610DI-35 vs EP610DC35 Comparación
Comparación detallada lado a lado de EP610DI-35 por Intel y EP610DC35 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP610DI-35 - 16-Macrocell Classic EPLD, 35ns, 5V, 24-CDIP | Intel / Altera
EP610DI-35 ObsoleteComparación de especificaciones
| Parámetro | EP610DI-35 | EP610DC35 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,85 | $19,20 |
| Family | Altera Classic EPLD | Classic EPLD |
| Series | EP610 | — |
| Logic Cells / Macrocells | 16 macrocells | — |
| Usable Gates | 300 | 300 |
| Product Terms | 160 | — |
| I/O Pins | 16 bidirectional | [DATA_NEEDED: number of user I/O pins] |
| Total Inputs | 20 (including 4 dedicated inputs) | — |
| Propagation Delay (tpd) | 35 ns | — |
| Maximum Toggle Frequency | 28.6 MHz | — |
| Internal Pipelined Data Rate | Up to 100 MHz | — |
| Tensión de alimentación | 5 V | 5 V |
| Technology | CMOS, UV-erasable | UV-erasable CMOS EPROM |
| Encapsulado | 24-pin CDIP (Ceramic DIP) | 24-pin CDIP (Ceramic DIP) with quartz erase window |
| Tipo de montaje | Through-hole | Through-Hole |
| Temperatura de funcionamiento | [DATA_NEEDED: industrial/commercial grade range] | [DATA_NEEDED: operating temperature range] |
| Estado RoHS | [DATA_NEEDED: not confirmed in supplied web data] | [DATA_NEEDED: RoHS status] |
| Logic Elements | — | 16 macrocells |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Frequency | — | 28.6 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Recuento de pines | — | 24 |
| Programming Method | — | Altera legacy programmer (PLDLMax or compatible) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |