EP610PC-25T vs EP610IPC-25 Comparación
Comparación detallada lado a lado de EP610PC-25T por Intel y EP610IPC-25 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
EP610PC-25T ⚠ Última compraComparación de especificaciones
| Parámetro | EP610PC-25T | EP610IPC-25 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $28,95 | $8,85 |
| Manufacturer | Intel (formerly Altera) | — |
| Distributor / Stocking Source | Rochester Electronics, LLC | — |
| Device Family | Altera Classic EPLD - EP610 | — |
| Device Type | Erasable Programmable Logic Device (EPLD, OTP for plastic package) | — |
| Logic Capacity | 300 usable gates | Equivalent to ~24 standard 24-pin PALs |
| Macro Cells | 16 | — |
| Registers | 16 | — |
| User I/Os | 16 | — |
| Propagation Delay (tPD) | 25 ns (speed grade 25) | — |
| Maximum Toggle Frequency | [DATA_NEEDED: max fmax] | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V |
| Process Technology | ECMOS (CMOS, EPROM-based) | — |
| Encapsulado | PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) | 24-pin PDIP (Plastic DIP) |
| Pinout Compatibility | Pin-compatible with EP610DC-25 (CERDIP-24, windowed) | — |
| Temperatura de funcionamiento | 0 °C to +70 °C (commercial) | 0 °C to +70 °C (Commercial) |
| Programming Method | OTP (one-time programmable) via Altera programming hardware | — |
| Tipo de montaje | Through-hole | Through-Hole |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (contains Pb, PDIP package) |
| Shipping Form (T suffix) | Tube | — |
| Family | — | Classic EPLD (EP610) |
| Architecture | — | PAL-type, CMOS, Erasable |
| Propagation Delay (tpd) | — | 25 ns (max) |
| Maximum Inputs | — | 20 |
| Maximum I/O Pins | — | 16 |
| Dedicated Outputs | — | 16 |
| Product Terms | — | 160 |
| Technology | — | CMOS, UV-erasable (windowless in IPC pkg) |
| TTL Compatibility | — | 100% TTL emulation |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |