EP610PC-35 vs EP610PC-25 Comparación
Comparación detallada lado a lado de EP610PC-35 por Rochester Electronics y EP610PC-25 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Rochester Electronics
EP610PC-35 - 16-Macrocell Classic EPLD, 35ns tPD | Rochester
EP610PC-35 ✓ ActivoComparación de especificaciones
| Parámetro | EP610PC-35 | EP610PC-25 |
|---|---|---|
| Marca | Rochester Electronics | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $16,79 | $9,75 |
| Device Type | EPLD (Erasable Programmable Logic Device) | OT PLD, PAL-type, CMOS |
| Family | Classic EPLD | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 37 ns (max, -35 speed grade) | — |
| Internal Counter Frequency | up to 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Supply Voltage - Internal | 4.75 V to 5.25 V | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature grade] |
| Programmable Type | EPLD (UV-erasable window variant: EP610DC; plastic OTP) | — |
| Encapsulado | 24-pin PDIP (Plastic DIP, 0.600" wide, through-hole) | PDIP-24 (0.3 inch, through-hole) |
| Tipo de montaje | Through Hole | Through-Hole (DIP) |
| Supplier Device Package | 24-PDIP | — |
| Logic Family | CMOS | — |
| Estado RoHS | [DATA_NEEDED: RoHS status - not confirmed in provided data] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Device Family | — | Classic EPLD (EP610 series) |
| Macro Cells | — | 16 |
| Propagation Delay (tpd) | — | 25 ns |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Technology | — | CMOS, EPROM (UV-erasable) |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 20 (bidirectional, JTAG-programmable OE per macrocell) |
| Programming Method | — | EPROM (UV-erasable), via Altera programming hardware |