EP910DC-15 vs EP910DM883B Comparación
Comparación detallada lado a lado de EP910DC-15 por Altera y EP910DM883B por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910DC-15 | EP910DM883B |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,75 | $7,10 |
| Family | Altera Classic EPLD | Classic EPLD - EP910 Series |
| Device Density | 900 usable gates | — |
| Macrocells | 24 | 24 |
| Logic Elements | [DATA_NEEDED: exact LE count] | Combinational + Registered |
| Dedicated Inputs | 12 | — |
| Bidirectional I/O Pins | 12 | — |
| Flip-Flops | 10 | — |
| Product Terms per Macrocells | 24 | — |
| Maximum Propagation Delay (tPD) | 15 ns | — |
| Speed Grade | 15 | — |
| Supply Voltage (VCC) | 5 V (typical) | 5 V |
| Temperatura de funcionamiento | 0C to +70C (commercial) | -55 °C to +125 °C (military) |
| Technology | CMOS EPROM, UV-erasable | — |
| Encapsulado | 24-pin ceramic DIP (DC) | CDIP-40 (Ceramic DIP, 40-pin) |
| Tipo de montaje | Through-Hole | Through-Hole (DIP) |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Estado RoHS | [DATA_NEEDED: not explicitly stated in verified data] | [DATA_NEEDED: RoHS status] |
| Manufacturer | — | Altera (now part of Intel) |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Architecture | — | PAL-type AND-OR-NOT, CMOS |
| Inputs | — | 36 |
| Outputs | — | 24 |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 40 ns (typical) |
| Frecuencia de reloj máxima | — | 25 MHz |
| Programming Voltage (VPP) | — | 12.5 V (UV-erase window) |
| MIL Processing | — | MIL-STD-883B Class B |
| Configuration Memory | — | UV-erasable EPROM |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |