EP910DC-15 vs EP910DM883B Comparaison
Comparaison détaillée côte à côte de EP910DC-15 par Altera et EP910DM883B par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910DC-15 | EP910DM883B |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $10,75 | $7,10 |
| Family | Altera Classic EPLD | Classic EPLD - EP910 Series |
| Device Density | 900 usable gates | — |
| Macrocells | 24 | 24 |
| Logic Elements | [DATA_NEEDED: exact LE count] | Combinational + Registered |
| Dedicated Inputs | 12 | — |
| Bidirectional I/O Pins | 12 | — |
| Flip-Flops | 10 | — |
| Product Terms per Macrocells | 24 | — |
| Maximum Propagation Delay (tPD) | 15 ns | — |
| Speed Grade | 15 | — |
| Supply Voltage (VCC) | 5 V (typical) | 5 V |
| Température de fonctionnement | 0C to +70C (commercial) | -55 °C to +125 °C (military) |
| Technology | CMOS EPROM, UV-erasable | — |
| Boîtier | 24-pin ceramic DIP (DC) | CDIP-40 (Ceramic DIP, 40-pin) |
| Type de montage | Through-Hole | Through-Hole (DIP) |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Statut RoHS | [DATA_NEEDED: not explicitly stated in verified data] | [DATA_NEEDED: RoHS status] |
| Manufacturer | — | Altera (now part of Intel) |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Architecture | — | PAL-type AND-OR-NOT, CMOS |
| Inputs | — | 36 |
| Outputs | — | 24 |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 40 ns (typical) |
| Fréquence d'horloge maximale | — | 25 MHz |
| Programming Voltage (VPP) | — | 12.5 V (UV-erase window) |
| MIL Processing | — | MIL-STD-883B Class B |
| Configuration Memory | — | UV-erasable EPROM |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |