EP910DC-30 vs EP910DM-40 Comparación
Comparación detallada lado a lado de EP910DC-30 por Intel y EP910DM-40 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910DC-30 | EP910DM-40 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $15,60 | $21,00 |
| Family | Classic EPLD (EP910 series) | Altera Classic EP910 |
| Architecture | PAL-type AND-OR sum-of-products, CMOS | PAL-type AND/OR with global programmable interconnect bus |
| Gate Count | 900 usable gates | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 30 ns (max) | 40 ns |
| Clock Frequency (fCNT) | 33.3 MHz | — |
| Dedicated Inputs | 36 | 36 |
| Outputs (Macrocells) | 24 | — |
| External Clock Pins | 2 (CLK1, CLK2) | — |
| Tensión de alimentación | 5 V | 5 V |
| Process Technology | CMOS | CMOS |
| Programming Method | UV-Erasable / OTP | — |
| Encapsulado | DIP-40 (through-hole, 600 mil) | 40-pin Ceramic DIP (Cerdip) with UV window |
| Temperatura de funcionamiento | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Tipo de montaje | Through-Hole | Through-Hole (DIP) |
| Product Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Dedicated Outputs | — | 24 |
| Bidirectional I/O Lines | — | 24 |
| Product Terms | — | 240 |
| External Clocks | — | 2 |
| Estado RoHS | — | [DATA_NEEDED: RoHS compliance status] |
| Programming Interface | — | JEDEC-standard fuse-map / UV erasure |