EP910DC-30 vs EP910DM-40 Comparison
Detailed side-by-side comparison of EP910DC-30 by Intel and EP910DM-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910DC-30 | EP910DM-40 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Classic EPLD (EP910 series) | Altera Classic EP910 |
| Architecture | PAL-type AND-OR sum-of-products, CMOS | PAL-type AND/OR with global programmable interconnect bus |
| Gate Count | 900 usable gates | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 30 ns (max) | 40 ns |
| Clock Frequency (fCNT) | 33.3 MHz | — |
| Dedicated Inputs | 36 | 36 |
| Outputs (Macrocells) | 24 | — |
| External Clock Pins | 2 (CLK1, CLK2) | — |
| Supply Voltage | 5 V | 5 V |
| Process Technology | CMOS | CMOS |
| Programming Method | UV-Erasable / OTP | — |
| Package | DIP-40 (through-hole, 600 mil) | 40-pin Ceramic DIP (Cerdip) with UV window |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Mounting Type | Through-Hole | Through-Hole (DIP) |
| Product Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Dedicated Outputs | — | 24 |
| Bidirectional I/O Lines | — | 24 |
| Product Terms | — | 240 |
| External Clocks | — | 2 |
| RoHS Status | — | [DATA_NEEDED: RoHS compliance status] |
| Programming Interface | — | JEDEC-standard fuse-map / UV erasure |