EP910IDC-15 vs EP910IPC-15 Comparación
Comparación detallada lado a lado de EP910IDC-15 por Altera y EP910IPC-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910IDC-15 | EP910IPC-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $7,95 |
| Manufacturer | Altera (now Intel PSG) | — |
| Family | Classic EPLD | — |
| Equivalent Gates | 450 | — |
| Macrocells | 24 | 24 |
| Flip-Flops | 48 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Maximum Frequency (fCNT) | 66.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V |
| Encapsulado | 40-pin CDIP (Ceramic DIP, through-hole) | PDIP-40 (Plastic DIP, 40-pin) |
| Terminal Count | 40 | — |
| Terminal Form | Through-Hole | — |
| Temperature Grade | Commercial (0C to +70C) | — |
| Programmable Security Bit | Yes | — |
| On-board Test Circuitry | Yes | — |
| Logic Type | UV Erasable EPROM-based | — |
| I/O Pins | 24 | 24 |
| Dedicated Inputs | 10 | 12 |
| Programming Technology | EPROM (UV-erasable) | — |
| Estado RoHS | non_compliant (ceramic DIP contains lead) | [DATA_NEEDED: rohs status not confirmed in verified data] |
| Device Family | — | Altera Classic EPLD (EP910 series) |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| Architecture | — | PAL-type, CMOS |
| Product Terms | — | 240 |
| External Clocks | — | 2 |
| Propagation Delay (tPD) | — | 15 ns |
| Temperatura de funcionamiento | — | 0C to +70C (commercial, IPC suffix) |
| Tipo de montaje | — | Through-Hole |
| Process Technology | — | CMOS |
| Programming Method | — | JEDEC fuse map via Altera EPLD programmer |
| Recuento de pines | — | 40 |