EP910IDC-15 vs EP910IPC-15 Comparaison
Comparaison détaillée côte à côte de EP910IDC-15 par Altera et EP910IPC-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910IDC-15 | EP910IPC-15 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,95 | $7,95 |
| Manufacturer | Altera (now Intel PSG) | — |
| Family | Classic EPLD | — |
| Equivalent Gates | 450 | — |
| Macrocells | 24 | 24 |
| Flip-Flops | 48 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Maximum Frequency (fCNT) | 66.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V |
| Boîtier | 40-pin CDIP (Ceramic DIP, through-hole) | PDIP-40 (Plastic DIP, 40-pin) |
| Terminal Count | 40 | — |
| Terminal Form | Through-Hole | — |
| Temperature Grade | Commercial (0C to +70C) | — |
| Programmable Security Bit | Yes | — |
| On-board Test Circuitry | Yes | — |
| Logic Type | UV Erasable EPROM-based | — |
| I/O Pins | 24 | 24 |
| Dedicated Inputs | 10 | 12 |
| Programming Technology | EPROM (UV-erasable) | — |
| Statut RoHS | non_compliant (ceramic DIP contains lead) | [DATA_NEEDED: rohs status not confirmed in verified data] |
| Device Family | — | Altera Classic EPLD (EP910 series) |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| Architecture | — | PAL-type, CMOS |
| Product Terms | — | 240 |
| External Clocks | — | 2 |
| Propagation Delay (tPD) | — | 15 ns |
| Température de fonctionnement | — | 0C to +70C (commercial, IPC suffix) |
| Type de montage | — | Through-Hole |
| Process Technology | — | CMOS |
| Programming Method | — | JEDEC fuse map via Altera EPLD programmer |
| Nombre de broches | — | 40 |