EP910ILC-25 vs EP910ILC-15N Comparación
Comparación detallada lado a lado de EP910ILC-25 por Intel y EP910ILC-15N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N ObsoleteComparación de especificaciones
| Parámetro | EP910ILC-25 | EP910ILC-15N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $9,85 |
| Family | EP910 Classic EPLD | Classic |
| Macrocells | 24 | — |
| User I/O Pins | 36 | 36 |
| Propagation Delay (tPD) | 25 ns | — |
| Internal Frequency (fMAX) | [DATA_NEEDED: fMAX rating] | — |
| Logic Blocks | Sum-of-products AND/OR array | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Configuration Memory | Non-volatile EPROM (windowed ceramic) | — |
| Encapsulado | 44-pin JLCC (windowed ceramic) | PLCC-44 (J-lead, surface mount) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | -40C to +85C (industrial) | 0 C to +70 C (commercial) |
| Tensión de alimentación | 5 V | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| Estado RoHS | non_compliant (ceramic windowed package) | Compliant |
| Estado del ciclo de vida | Obsolete - last time buy was late 1990s | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Gates | — | 450 |
| Macro Cells | — | 24 |
| Maximum Propagation Delay (tPD) | — | 15 ns |
| Maximum Operating Frequency | — | 66.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Dedicated Input Pins | — | 16 |
| Process Technology | — | CMOS EPROM (one-time programmable) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Programming | — | EPROM / JTAG (Classic EP-series) |