EP910IPC-50 vs EP910IPC-25 Comparación
Comparación detallada lado a lado de EP910IPC-50 por Altera y EP910IPC-25 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910IPC-50 | EP910IPC-25 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $13,85 | $10,40 |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EPLD | Classic EPLD (EP910 series) |
| Logic Capacity | [DATA_NEEDED: macrocell count / equivalent gates] | — |
| Propagation Delay (tPD) | 50 ns | 25 ns |
| Clock-to-Output (tCO) | 35 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: fMAX] | — |
| User I/O Pins | 24 | — |
| Encapsulado | 40-pin Ceramic DIP (IPC, windowed) | 40-pin PDIP (PDIP-40) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Temperatura de funcionamiento | -40C to +85C (industrial) | 0C to +70C (commercial grade) |
| Technology | CMOS EPROM cell | — |
| Programming Method | Off-board EPROM programmer + UV erase | EPROM cell (OTP / UV erasable) |
| Erasure Method | UV light through ceramic window (IPC package) | — |
| Tipo de montaje | Through-Hole (DIP) | Through-Hole |
| Estado RoHS | [DATA_NEEDED: not stated in verified data] | — |
| Manufacturer | — | Altera (now Intel) |
| Architecture | — | PAL-type EPLD, CMOS, UV/OTP |
| Usable Gates | — | 450 |
| Macrocells | — | 24 |
| Product Terms | — | 240 |
| Maximum Frequency (fMAX) | — | 40 MHz |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Lines | — | 24 |
| Total Inputs (max) | — | 36 |
| Total Outputs (max) | — | 24 |
| Development Tool | — | MAX+PLUS II |