EP910LC-30Y vs EP910LC-30 Comparación
Comparación detallada lado a lado de EP910LC-30Y por Altera y EP910LC-30 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910LC-30Y | EP910LC-30 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $25,40 | $22,50 |
| Family | Altera Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 24 | — |
| Usable Gates | 450 | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Counter Frequency (fMAX) | 100 MHz (family maximum) | — |
| Tensión de alimentación | 5 V (TTL-compatible) | — |
| Process Technology | CMOS, UV-erasable / OTP | CMOS (EPROM-based) |
| Encapsulado | PLCC-44 | — |
| Temperatura de funcionamiento | Commercial 0C to +70C | — |
| Speed/Power Grade | LC (low-power, 30ns) | — |
| Processing Flow | Y (extended reliability) | — |
| Logic Compatibility | 100% TTL emulation | — |
| Tipo de montaje | Surface Mount (PLCC socket) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status not specified in retrieved data] | [DATA_NEEDED: RoHS status] |
| Macrocell Count | — | 24 |
| Propagation Delay (tPD) | — | 30 ns (max) |
| Maximum Toggle Frequency | — | 62 MHz |
| Supply Voltage (VCC) | — | 5 V (nominal, TTL) |
| Package Type | — | PDIP-40 (Plastic DIP, through-hole) |
| Operating Temperature Grade | — | Commercial (0C to +70C) |
| I/O Pin Count | — | 24 |
| Dedicated Input Pins | — | 36 (including I/O) |
| Product Terms per Macrocell | — | Up to 16 |
| Programming Technology | — | UV-erasable EPROM cell |
| Development Tool | — | Altera MAX+PLUS II |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |