EP910LC-30Y vs EP910LC-30 对比

详细并排对比 EP910LC-30Y 出自 Altera 和 EP910LC-30 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP910LC-30Y EP910LC-30
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $25.40 $22.50
Family Altera Classic EPLD —
Device Type EPLD (Erasable Programmable Logic Device) EPLD (Erasable Programmable Logic Device)
Macrocells 24 —
Usable Gates 450 —
Pin-to-Pin Delay (tPD) 30 ns —
Counter Frequency (fMAX) 100 MHz (family maximum) —
电源电压 5 V (TTL-compatible) —
Process Technology CMOS, UV-erasable / OTP CMOS (EPROM-based)
封装 PLCC-44 —
工作温度 Commercial 0C to +70C —
Speed/Power Grade LC (low-power, 30ns) —
Processing Flow Y (extended reliability) —
Logic Compatibility 100% TTL emulation —
安装类型 Surface Mount (PLCC socket) —
RoHS 状态 [DATA_NEEDED: RoHS status not specified in retrieved data] [DATA_NEEDED: RoHS status]
Macrocell Count — 24
Propagation Delay (tPD) — 30 ns (max)
Maximum Toggle Frequency — 62 MHz
Supply Voltage (VCC) — 5 V (nominal, TTL)
Package Type — PDIP-40 (Plastic DIP, through-hole)
Operating Temperature Grade — Commercial (0C to +70C)
I/O Pin Count — 24
Dedicated Input Pins — 36 (including I/O)
Product Terms per Macrocell — Up to 16
Programming Technology — UV-erasable EPROM cell
Development Tool — Altera MAX+PLUS II
MSL 等级 — [DATA_NEEDED: MSL level]

数据手册与资源

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