EP910LC-35T vs EP910LC44-35 Comparación
Comparación detallada lado a lado de EP910LC-35T por Altera y EP910LC44-35 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910LC-35T | EP910LC44-35 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $28,90 | $19,95 |
| Family | Classic EPLD (EP910) | Classic EPLD (OT sub-family) |
| Logic Capacity | 450 usable gates | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 35 ns | 35 ns (max) |
| Maximum Operating Frequency | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V (single supply) |
| User I/O Pins | 36 | — |
| Encapsulado | PLCC-44 (J-lead) | 44-pin PLCC (J-leaded) |
| Process Technology | CMOS (EPROM-based) | CMOS |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Erasure Method | UV-erasable window (ceramic package) / OTP (plastic) | — |
| Programming | Altera programming hardware + MAX+PLUS II | — |
| Tipo de montaje | Surface Mount (PLCC socket or solder) | Surface Mount |
| Nivel MSL | MSL 3 (168 hours) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status not in verified data] | — |
| Architecture | — | PAL-type AND/OR array |
| Usable Gates | — | 450 |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Total Inputs | — | 36 |
| I/O Pins | — | 24 |
| Global Clocks | — | 2 |
| Programmability | — | UV-erasable (windowed ceramic) |