EP910LI-15 vs EP910LI-50 Comparación
Comparación detallada lado a lado de EP910LI-15 por Altera y EP910LI-50 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910LI-15 | EP910LI-50 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,70 | $65,00 |
| Product Type | Programmable Logic Device (PLD) | — |
| Device Family | Altera Classic EPLD | — |
| Part Number | EP910LI-15 | — |
| Supply Voltage Range | 4.5 V to 5.5 V | — |
| Dedicated Inputs | 12 | — |
| Input/Output Lines | 24 | — |
| Total User-Signal Resources | 36 | — |
| Speed Grade | 15 ns | — |
| Rango de temperatura de funcionamiento | -40 °C to +85 °C | — |
| Technology | CMOS | CMOS, UV-erasable EPROM |
| Encapsulado | 44-terminal J-lead ceramic chip carrier (PQCC44) | — |
| Package Pin Count | 44 terminals | 40 |
| Package Mounting | Surface Mount | — |
| Dielectric/Construction | Ceramic | — |
| Estado RoHS | unknown | [DATA_NEEDED: RoHS status] |
| REACH Status | unknown | — |
| AEC-Q100 Status | not_applicable | — |
| Lead-Free Status | unknown | — |
| Halogen-Free Status | unknown | — |
| Conflict Minerals Status | unknown | — |
| Family | — | Altera Classic EPLD |
| Macrocells | — | 24 |
| Usable Gates | — | 450 |
| Propagation Delay (tPD) | — | 50 ns |
| Package Type | — | CERDIP-40 (L) |
| Supply Voltage (VCC) | — | 5 V +/- 10% |
| Temperatura de funcionamiento | — | -40C to +85C (industrial) |
| Logic Blocks | — | Classic AND/OR array architecture |
| I/O Pins | — | [DATA_NEEDED: I/O pin count] |
| Programming Method | — | EPROM programmer (UV-erasable window) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Speed Grade Suffix | — | -50 (50 ns tPD) |