EP910LI-20 vs EP910IPC-12 Comparación
Comparación detallada lado a lado de EP910LI-20 por Altera y EP910IPC-12 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910LI-20 | EP910IPC-12 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $19,95 | $14,20 |
| Family | Altera Classic EPLD | Classic EPLD |
| Macrocells | 24 | 24 |
| Maximum Operating Frequency | 62 MHz | — |
| Propagation Delay (tpd) | 20 ns | — |
| Dedicated Inputs | 16 | 10 |
| I/O Pins | 24 | 24 |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| Temperatura de funcionamiento | -40C to +85C (Industrial) | -40C to +85C (industrial) |
| Encapsulado | 40-pin Ceramic DIP (Windowed) | 40-pin PDIP |
| Technology | CMOS, UV-erasable | CMOS EPLD (UV-erasable or OTP) |
| Package Type | Through-Hole, Ceramic DIP with Quartz Window | — |
| Temperature Grade | Industrial (-40C to +85C) | — |
| Recuento de pines | 40 | — |
| Logic Family | EPLD (Erasable PLD) | — |
| Architecture | Sum-of-products macrocell | — |
| Pin/Package Compatibility | Pin-compatible across EP910 family | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Usable Gates | — | 450 |
| Maximum Operating Frequency (fMAX) | — | 76.9 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 12 ns |
| Tipo de montaje | — | Through Hole |
| Programming Toolchain | — | MAX+PLUS II |
| Logic Capacity | — | Equivalent to ~24 PAL16V8s |