EP910LI-35 vs EP910LI-40 Comparación
Comparación detallada lado a lado de EP910LI-35 por Altera y EP910LI-40 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910LI-35 | EP910LI-40 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $25,80 | $12,90 |
| Family | Altera Classic EPLD | — |
| Device Series | EP910 | — |
| Usable Gates | 900 | — |
| Macrocells | 24 | 24 |
| Maximum User I/O Pins | 38 | — |
| Propagation Delay (t_PD) | 35 ns | — |
| Maximum Counter Frequency (f_CNT) | 76.9 MHz | — |
| Tensión de alimentación | 5 V (4.75 V to 5.25 V) | — |
| Temperatura de funcionamiento | -40 °C to +85 °C (Industrial) | -40C to +85C (industrial, I-suffix) |
| Encapsulado | 44-pin PLCC (J-lead) | PLCC-44 (J-lead, windowed ceramic) |
| Process Technology | CMOS EPROM | — |
| Programming Technology | EPROM (UV-erasable) | — |
| Erase/Program Cycles | ≥100 | — |
| Tipo de montaje | Surface Mount | Surface Mount (socket-compatible) |
| Lead Pitch | 1.27 mm | — |
| Manufacturer | — | Altera (now Intel PSG) |
| Product Family | — | Classic EPLD - EP910 series |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 bidirectional |
| Maximum Logic Inputs | — | 36 |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 40 ns |
| Technology | — | Low-power CMOS (L-suffix) |
| Programmability | — | UV-erasable, JEDEC-standard algorithm |
| Estado RoHS | — | Non-compliant (windowed ceramic PLCC, legacy) |
| Lifecycle | — | Obsolete - replaced by MAX 7000 / MAX II CPLD family |