EP910LI-35 vs EP910LI-40 비교
다음의 상세 나란히 비교: EP910LI-35 제조: Altera 및 EP910LI-40 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP910LI-35 | EP910LI-40 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | NRND | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $25.80 | $12.90 |
| Family | Altera Classic EPLD | — |
| Device Series | EP910 | — |
| Usable Gates | 900 | — |
| Macrocells | 24 | 24 |
| Maximum User I/O Pins | 38 | — |
| Propagation Delay (t_PD) | 35 ns | — |
| Maximum Counter Frequency (f_CNT) | 76.9 MHz | — |
| 공급 전압 | 5 V (4.75 V to 5.25 V) | — |
| 동작 온도 | -40 °C to +85 °C (Industrial) | -40C to +85C (industrial, I-suffix) |
| 패키지 | 44-pin PLCC (J-lead) | PLCC-44 (J-lead, windowed ceramic) |
| Process Technology | CMOS EPROM | — |
| Programming Technology | EPROM (UV-erasable) | — |
| Erase/Program Cycles | ≥100 | — |
| 실장 유형 | Surface Mount | Surface Mount (socket-compatible) |
| Lead Pitch | 1.27 mm | — |
| Manufacturer | — | Altera (now Intel PSG) |
| Product Family | — | Classic EPLD - EP910 series |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 bidirectional |
| Maximum Logic Inputs | — | 36 |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 40 ns |
| Technology | — | Low-power CMOS (L-suffix) |
| Programmability | — | UV-erasable, JEDEC-standard algorithm |
| RoHS 상태 | — | Non-compliant (windowed ceramic PLCC, legacy) |
| Lifecycle | — | Obsolete - replaced by MAX 7000 / MAX II CPLD family |