EP910LI-40T vs EP910LI-40 Comparación
Comparación detallada lado a lado de EP910LI-40T por Intel y EP910LI-40 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910LI-40T | EP910LI-40 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,75 | $12,90 |
| Family | Classic EPLD | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | 24 bidirectional |
| Maximum Inputs | 36 | — |
| Maximum Outputs | 24 | — |
| Product Terms | 240 | 240 |
| Propagation Delay (tPD) | 40 ns | 40 ns |
| Technology | CMOS, UV-erasable EPROM | Low-power CMOS (L-suffix) |
| Tensión de alimentación | 5 V (typical) | — |
| Temperatura de funcionamiento | -40C to +85C (Industrial) | -40C to +85C (industrial, I-suffix) |
| Architecture | PAL-type with global bus | — |
| Encapsulado | Tape and Reel (suffix T); 40-pin DIP / 44-pin PLCC | PLCC-44 (J-lead, windowed ceramic) |
| Estado RoHS | [DATA_NEEDED: rohs status] | Non-compliant (windowed ceramic PLCC, legacy) |
| Programming Method | Altera Master Programming Unit (MPU), no JTAG | — |
| Manufacturer | — | Altera (now Intel PSG) |
| Product Family | — | Classic EPLD - EP910 series |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Maximum Logic Inputs | — | 36 |
| Tipo de montaje | — | Surface Mount (socket-compatible) |
| Programmability | — | UV-erasable, JEDEC-standard algorithm |
| Lifecycle | — | Obsolete - replaced by MAX 7000 / MAX II CPLD family |