EP910LI-40T vs EP910LI-40 Comparison
Detailed side-by-side comparison of EP910LI-40T by Intel and EP910LI-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LI-40T | EP910LI-40 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $12.90 |
| Family | Classic EPLD | β |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | 24 bidirectional |
| Maximum Inputs | 36 | β |
| Maximum Outputs | 24 | β |
| Product Terms | 240 | 240 |
| Propagation Delay (tPD) | 40 ns | 40 ns |
| Technology | CMOS, UV-erasable EPROM | Low-power CMOS (L-suffix) |
| Supply Voltage | 5 V (typical) | β |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C (industrial, I-suffix) |
| Architecture | PAL-type with global bus | β |
| Package | Tape and Reel (suffix T); 40-pin DIP / 44-pin PLCC | PLCC-44 (J-lead, windowed ceramic) |
| RoHS Status | [DATA_NEEDED: rohs status] | Non-compliant (windowed ceramic PLCC, legacy) |
| Programming Method | Altera Master Programming Unit (MPU), no JTAG | β |
| Manufacturer | β | Altera (now Intel PSG) |
| Product Family | β | Classic EPLD - EP910 series |
| Device Type | β | Erasable Programmable Logic Device (EPLD) |
| Maximum Logic Inputs | β | 36 |
| Mounting Type | β | Surface Mount (socket-compatible) |
| Programmability | β | UV-erasable, JEDEC-standard algorithm |
| Lifecycle | β | Obsolete - replaced by MAX 7000 / MAX II CPLD family |