EP910PC-15T vs EP910DC-15 Comparación
Comparación detallada lado a lado de EP910PC-15T por Altera y EP910DC-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910PC-15T | EP910DC-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $14,20 | $10,75 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocell Count | 24 | — |
| Dedicated Input Pins | 10 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Speed Grade | -15 (15 ns) | 15 |
| Supply Voltage (VCC) | 5 V (nominal) | 5 V (typical) |
| Technology | CMOS, UV-erasable / OTP | CMOS EPROM, UV-erasable |
| Encapsulado | 40-pin PDIP (Plastic DIP) | 24-pin ceramic DIP (DC) |
| Tipo de montaje | Through-hole (DIP) | Through-Hole |
| Output Drive Current | [DATA_NEEDED: IOL per output] | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Logic Capacity | 24 macrocells / 72 product terms (typical Classic architecture) | — |
| Programming Method | JEDEC fuse map via Altera LogicMap / MAX+PLUS II | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not explicitly stated in verified data] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Security Bit | Yes (design protection) | — |
| Tape and Reel | Yes (suffix T) | — |
| Device Density | — | 900 usable gates |
| Macrocells | — | 24 |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Pins | — | 12 |
| Flip-Flops | — | 10 |
| Product Terms per Macrocells | — | 24 |
| Maximum Propagation Delay (tPD) | — | 15 ns |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |