EP910PC-15T vs EP910DC-15 Сравнение
Подробное сравнение бок о бок EP910PC-15T от Altera и EP910DC-15 от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EP910PC-15T | EP910DC-15 |
|---|---|---|
| Бренд | Altera | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Obsolete | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $14,20 | $10,75 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocell Count | 24 | — |
| Dedicated Input Pins | 10 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Speed Grade | -15 (15 ns) | 15 |
| Supply Voltage (VCC) | 5 V (nominal) | 5 V (typical) |
| Technology | CMOS, UV-erasable / OTP | CMOS EPROM, UV-erasable |
| Корпус | 40-pin PDIP (Plastic DIP) | 24-pin ceramic DIP (DC) |
| Тип монтажа | Through-hole (DIP) | Through-Hole |
| Output Drive Current | [DATA_NEEDED: IOL per output] | — |
| Рабочая температура | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Logic Capacity | 24 macrocells / 72 product terms (typical Classic architecture) | — |
| Programming Method | JEDEC fuse map via Altera LogicMap / MAX+PLUS II | — |
| Статус RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not explicitly stated in verified data] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Security Bit | Yes (design protection) | — |
| Tape and Reel | Yes (suffix T) | — |
| Device Density | — | 900 usable gates |
| Macrocells | — | 24 |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Pins | — | 12 |
| Flip-Flops | — | 10 |
| Product Terms per Macrocells | — | 24 |
| Maximum Propagation Delay (tPD) | — | 15 ns |
| Уровень MSL | — | [DATA_NEEDED: MSL level] |