EP910PC-20T vs EP610PC-20T Comparación
Comparación detallada lado a lado de EP910PC-20T por Altera y EP610PC-20T por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910PC-20T | EP610PC-20T |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Unknown | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $8,70 | $7,20 |
| Device Type | EPLD | — |
| Family | Classic EPLD | Classic EPLD |
| Fabrication Technology | CMOS | — |
| Logic Integration | 300 to 900 usable gates | — |
| Logic Emulation | 100% TTL emulation | — |
| Application Function | High-speed, low-power logic integration | — |
| Programmable Device Class | Erasable programmable logic device | — |
| Device Family | Altera Classic EPLD Family | — |
| Speed Grade | 20 ns | — |
| Package Code | PC | — |
| Package Pin Count | [DATA_NEEDED: package pin count] | — |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| Tensión de alimentación | [DATA_NEEDED: operating supply voltage] | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | 0C to +70C (Commercial) |
| I/O Count | [DATA_NEEDED: I/O count] | — |
| Internal Logic Capacity | 300 to 900 usable gates | — |
| Supported Logic Integration | Multiple PAL- and GAL-type devices | — |
| Programming Interface | [DATA_NEEDED: programming interface] | — |
| Programming Voltage | [DATA_NEEDED: programming voltage] | — |
| Mounting Technology | [DATA_NEEDED: mounting technology] | — |
| Estado RoHS | unknown | unknown |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | not_applicable | — |
| Lead-Free Status | unknown | — |
| Halogen-Free Status | unknown | — |
| Logic Elements / Macrocells | — | 16 macrocells |
| Usable Gates | — | 300 gates |
| Propagation Delay (tPD) | — | 20 ns |
| Maximum Frequency (fMAX) | — | 62.5 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Number of Dedicated Inputs | — | 16 |
| Number of I/O Pins | — | 16 |
| Programmable Output Enable | — | Yes (per macrocell) |
| Encapsulado | — | 24-pin PDIP (Plastic DIP) |
| Tipo de montaje | — | Through-Hole |
| Programming Technology | — | UV-erasable EPROM, CMOS |
| Development Tool | — | MAX+PLUS II |