EP910PC-30 vs EP910PC-0 Comparación
Comparación detallada lado a lado de EP910PC-30 por Altera y EP910PC-0 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910PC-30 | EP910PC-0 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $6,50 | $8,70 |
| Family | Altera Classic EPLD | Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | ~450 | 900 gates |
| Pin-to-Pin Propagation Delay (tPD) | 30 ns | — |
| Maximum Counter Frequency (fCNT) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V ±10% | — |
| Logic Inputs | 36 dedicated | — |
| I/O Pins | 12 bidirectional | 24 |
| Logic Array Blocks (LABs) | 4 | — |
| Encapsulado | PDIP-40 (plastic DIP, 0.6 inch) | PDIP-40 (Plastic DIP, 40-pin) |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Technology | UV-erasable EPROM cell | — |
| TTL Emulation | 100% TTL-compatible | — |
| Power Dissipation | [DATA_NEEDED: power dissipation mW] | — |
| Estado RoHS | Non-compliant (contains lead, PDIP package) | — |
| Tipo de montaje | Through-hole DIP | Through-Hole (DIP) |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Blocks | — | 6 (4 macrocells each) |
| Dedicated Inputs | — | 10 |
| Speed Grade | — | -0 (slowest) |
| Tensión de alimentación | — | 5 V (single supply) |
| Process Technology | — | CMOS |
| Logic Compatibility | — | 100% TTL emulation |
| Programming Method | — | UV-erasable / OTP |