EP910PC-30 vs EP910PC-0 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PC-30 sa pamamagitan ng Altera at EP910PC-0 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PC-30 | EP910PC-0 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | ~450 | 900 gates |
| Pin-to-Pin Propagation Delay (tPD) | 30 ns | — |
| Maximum Counter Frequency (fCNT) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V ±10% | — |
| Logic Inputs | 36 dedicated | — |
| I/O Pins | 12 bidirectional | 24 |
| Logic Array Blocks (LABs) | 4 | — |
| Packhaging | PDIP-40 (plastic DIP, 0.6 inch) | PDIP-40 (Plastic DIP, 40-pin) |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Technology | UV-erasable EPROM cell | — |
| TTL Emulation | 100% TTL-compatible | — |
| Power Dissipation | [DATA_NEEDED: power dissipation mW] | — |
| Tindminan RoHS | Non-compliant (contains lead, PDIP package) | — |
| Uri ng Pagpapasok | Through-hole DIP | Through-Hole (DIP) |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Blocks | — | 6 (4 macrocells each) |
| Dedicated Inputs | — | 10 |
| Speed Grade | — | -0 (slowest) |
| Volte ng Pagbibigay | — | 5 V (single supply) |
| Process Technology | — | CMOS |
| Logic Compatibility | — | 100% TTL emulation |
| Programming Method | — | UV-erasable / OTP |