EPC1441TI32 vs EPC2-TI32N Comparación
Comparación detallada lado a lado de EPC1441TI32 por Altera y EPC2-TI32N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC1441TI32 | EPC2-TI32N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,30 | $11,50 |
| Tipo de memoria | OTP Configuration PROM | — |
| Tamaño de memoria | 440,800 x 1 bit (approximately 440 kb) | 1.6 Mb |
| Memory Organization | Serial, 1-bit data bus | 1,695,680 x 1 |
| Tensión de alimentación | 5.0 V | — |
| Access Time | 90 ns (approximately 10 MHz) | — |
| Configuration Interface | Altera Active Serial (AS) | — |
| Temperatura de funcionamiento | -40C to +85C (Industrial) | -40 C to +85 C |
| Encapsulado | 32-pin TQFP (7 x 7 mm) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Technology | CMOS OTP flash cell | Flash + CMOS configuration logic |
| Programmability | One-Time Programmable (OTP) | — |
| Supported FPGA Families | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX | — |
| Cascade Support | Yes (nCASC pin for multi-PROM chains) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Programmable Type | — | In System Programmable |
| Tipo de interfaz | — | Serial (for SRAM-based LUT FPGAs) |
| Programming Interface | — | IEEE 1532-compliant JTAG |
| Supply Voltage - VCCINT | — | 3.0 V to 3.6 V |
| Supply Voltage - VCCIO | — | 4.5 V to 5.5 V |
| Encapsulado / Carcasa | — | 32-TQFP (7 mm x 7 mm) |
| Terminal Pitch | — | 0.8 mm |
| Supplier Device Package | — | 32-TQFP |
| Packaging | — | Tray |
| Configuration Clock | — | Dedicated DCLK output for FPGA |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |