EPC144ILC-20 vs EPC1441LC20N Comparación
Comparación detallada lado a lado de EPC144ILC-20 por Altera y EPC1441LC20N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC144ILC-20 | EPC1441LC20N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $3,85 | $7,95 |
| Tipo de memoria | OTP Configuration PROM (one-time programmable) | OTP EPROM (One-Time Programmable) |
| Tamaño de memoria | 440 kb (kilobits) | 440 Kbit |
| Configuration Interface | Serial (Altera proprietary PS mode) | — |
| Tensión de alimentación | 5.0 V (typical) | 3.3 V (typical) |
| Standby Current | < 50 uA (CMOS standby) | — |
| Programmable | No (factory-programmed by Altera or distributor) | — |
| Encapsulado | 20-pin PLCC (J-lead) | 20-PLCC (J-Lead, 9 x 9 mm) |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (commercial) |
| Compatible FPGA Families | Cyclone, ACEX 1K, APEX 20K, MAX 7000-series | — |
| Configuration Mode Support | PS (passive serial) and FPP (fast passive parallel) | — |
| JTAG Interface | Not present | — |
| End-of-Life Status | Last-time-buy (per Altera product change notifications) | — |
| Lead-Free / RoHS | Depends on date code; non-RoHS vintage stock common | — |
| Programming Method | Altera dedicated PROM programmer hardware | — |
| Data Retention | Permanent (anti-fuse OTP cell, no retention concern) | — |
| Recuento de pines | 20 | — |
| Tipo de montaje | Surface Mount (PLCC J-lead) | Surface Mount (PLCC socket compatible) |
| Organización de memoria | — | 55 K x 8 bit |
| Interfaz | — | Serial, 4-wire (nCS, DCLK, DATA, nINIT_CONF) |
| Configuration Clock (DCLK) | — | 8 MHz maximum |
| Programming Interface | — | JTAG (IEEE 1149.1) / Altera Programming Unit |
| Supported FPGA Families | — | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| Cascadable | — | Yes (nCS daisy-chain) |
| Estado RoHS | — | [DATA_NEEDED: RoHS status] |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |