EPC144ILC20 vs EPC1LC20-W Comparación
Comparación detallada lado a lado de EPC144ILC20 por Intel y EPC1LC20-W por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC144ILC20 | EPC1LC20-W |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $9,85 |
| Manufacturer | Altera (now Intel) | — |
| Part Family | EPC144 - Configuration EPROM | — |
| Tipo de memoria | OTP CMOS Configuration EPROM (UV-erasable, factory OTP-programmed) | OTP (One-Time Programmable) Configuration PROM |
| Tamaño de memoria | 440,800 bit (54 KB) | 1 Mbit |
| Interfaz | Serial (Altera FLEX/MAX configuration - DCLK / DATA0 / nCONFIG / nSTATUS) | Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS) |
| Supply Voltage VCC | 5 V (nominal) | — |
| Encapsulado | PLCC-20 (Plastic Leaded Chip Carrier, JEDEC MS-018) | 20-PLCC J-lead (9x9 mm) |
| Rango de temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Configuration Mode | Master Serial / daisy-chain JTAG-style | — |
| Programmability | One-Time-Programmable (factory programmed by Altera with user bitstream) | — |
| JTAG Support | Yes (TDI/TDO pins for ByteBlasterMV / USB-Blaster ISP) | — |
| Compatible FPGAs | Altera EPF8282, EPF8452, EPF10K-series Classic FPGAs | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | Compliant (Pb-free -W finish) |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Tipo de montaje | Surface Mount (PLCC-20 socket or SMT land pattern) | Surface Mount (PLCC socket or direct solder) |
| Nivel MSL | [DATA_NEEDED: MSL rating] | — |
| Configuration Clock (DCLK) | — | 8 MHz maximum |
| Tensión de alimentación | — | 3.3 V and 5.0 V |
| In-System Programming | — | Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V |
| Lead Finish | — | Pb-free (matte tin) - "-W" suffix |
| Daisy-Chain Support | — | Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs |
| Compression Support | — | Yes - stores compressed Altera FPGA bitstreams |
| Programming Cycles | — | 1 (OTP) |
| Target FPGA Families | — | Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury |