EPC144ILC20 vs EPC1LC20-W Comparaison
Comparaison détaillée côte à côte de EPC144ILC20 par Intel et EPC1LC20-W par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC144ILC20 | EPC1LC20-W |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,95 | $9,85 |
| Manufacturer | Altera (now Intel) | — |
| Part Family | EPC144 - Configuration EPROM | — |
| Type de mémoire | OTP CMOS Configuration EPROM (UV-erasable, factory OTP-programmed) | OTP (One-Time Programmable) Configuration PROM |
| Taille de mémoire | 440,800 bit (54 KB) | 1 Mbit |
| Interface | Serial (Altera FLEX/MAX configuration - DCLK / DATA0 / nCONFIG / nSTATUS) | Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS) |
| Supply Voltage VCC | 5 V (nominal) | — |
| Boîtier | PLCC-20 (Plastic Leaded Chip Carrier, JEDEC MS-018) | 20-PLCC J-lead (9x9 mm) |
| Plage de température de fonctionnement | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Configuration Mode | Master Serial / daisy-chain JTAG-style | — |
| Programmability | One-Time-Programmable (factory programmed by Altera with user bitstream) | — |
| JTAG Support | Yes (TDI/TDO pins for ByteBlasterMV / USB-Blaster ISP) | — |
| Compatible FPGAs | Altera EPF8282, EPF8452, EPF10K-series Classic FPGAs | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | Compliant (Pb-free -W finish) |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Type de montage | Surface Mount (PLCC-20 socket or SMT land pattern) | Surface Mount (PLCC socket or direct solder) |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Configuration Clock (DCLK) | — | 8 MHz maximum |
| Tension d'alimentation | — | 3.3 V and 5.0 V |
| In-System Programming | — | Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V |
| Lead Finish | — | Pb-free (matte tin) - "-W" suffix |
| Daisy-Chain Support | — | Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs |
| Compression Support | — | Yes - stores compressed Altera FPGA bitstreams |
| Programming Cycles | — | 1 (OTP) |
| Target FPGA Families | — | Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury |