EPC16UC88T vs EPC16UC88 Comparación
Comparación detallada lado a lado de EPC16UC88T por Altera y EPC16UC88 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC16UC88T | EPC16UC88 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | EEPROM | Memory ICs |
| Estado del ciclo de vida | Última compra | Unknown |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $0,00 |
| Tipo de memoria | Non-volatile Flash configuration PROM (in-system programmable) | — |
| Memory Density | 16 Mbit (2,097,152 x 8 bits) | — |
| Configuration Interface | Serial (4-wire: nCS, DCLK, DATA, nINIT_CONF_DONE) | — |
| Maximum DCLK Frequency | 33 MHz | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (3.3 V nominal) | — |
| Rango de temperatura de funcionamiento | -40 C to +85 C (industrial) | — |
| Encapsulado | 88-ball UBGA, 11 mm x 8 mm | 88-UBGA (11x8) |
| In-System Programming | IEEE Std 1149.1 (JTAG) | — |
| Cascade Support | Yes (for higher density multi-PROM chains) | — |
| MSEL Compatibility | FPP / PS configuration modes (3.3 V legacy) | — |
| Compatible FPGA Families | Cyclone, Cyclone II, Stratix, Stratix II, Stratix III, Stratix IV, Arria GX | — |
| Family Density Step | Largest member of EPC4 / EPC8 / EPC16 family | — |
| Estado RoHS | [DATA_NEEDED: RoHS] | [DATA_NEEDED: RoHS status] |
| Nivel MSL | [DATA_NEEDED: MSL] | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free status] | — |
| Open-Drain nINIT_CONF_DONE | Yes | — |
| Device Type | — | In-system programmable configuration PROM for FPGAs |
| Configuration Memory Capacity | — | 16 Mb |
| Tensión de alimentación | — | 3.3 V core and I/O |
| Package Family | — | UBGA |
| In-System Programmability | — | IEEE Std. 1532 compatible |
| Programming Language Support | — | Jam Standard Test and Programming Language (STAPL) |
| JTAG Boundary Scan | — | Supported |
| nINIT_CONF Function | — | Allows private JTAG instruction to start FPGA configuration |
| Configuration Architecture | — | Configuration controller and flash memory |
| FPGA Configuration Use | — | Automatic configuration after power-up or system initialization |
| Data Output | — | Configuration data output controlled by OE and nCS |
| Output Control | — | OE and nCS control tri-state buffer and address counter |
| Tipo de montaje | — | Surface mount |
| Package Dimensions | — | 11 mm x 8 mm |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| Temperatura de funcionamiento | — | [DATA_NEEDED: operating temperature] |
| Output Current | — | [DATA_NEEDED: output current] |
| Configuration Frequency | — | [DATA_NEEDED: configuration frequency] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |