EPC18QI100 vs EPC16QI100TBAC Comparación
Comparación detallada lado a lado de EPC18QI100 por Altera y EPC16QI100TBAC por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPC16QI100TBAC - Altera Enhanced Configuration PROM 16Mb | FPGA
EPC16QI100TBAC ⚠ Última compraComparación de especificaciones
| Parámetro | EPC18QI100 | EPC16QI100TBAC |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,40 | $15,95 |
| Manufacturer | Altera (now Intel Programmable Solutions Group) | — |
| Device Type | FPGA Configuration PROM (nonvolatile) | — |
| Memory Density | 18 Mbit (18,874,368 bits) | 16 Mbit (2 Mbyte) |
| Configuration Interface | Altera serial (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5 V tolerant | — |
| Programming Interface | JTAG (IEEE 1149.1) in-system programmable | JTAG / 4-wire passive serial |
| Cascading Support | Yes (via nCASC pin, multi-device chains supported) | — |
| Encapsulado | 100-pin PQFP (Plastic Quad Flat Pack) | 100-pin PQFP (20 x 14 mm) |
| Package Dimensions | 14 mm x 20 mm x 1.4 mm (body) / 3.4 mm (overall incl. leads) | — |
| Rango de temperatura de funcionamiento | -40 C to +85 C (industrial) | — |
| Tipo de montaje | Surface Mount | Surface Mount (PQFP) |
| Nivel MSL | [DATA_NEEDED: MSL level] | 3 (168 hours) |
| Lead Finish | Matte tin (lead-free, per Altera Pb-free roadmap) | — |
| Estado RoHS | Compliant (Pb-free part marking) | — |
| Configuration Time | [DATA_NEEDED: configuration time at typical DCLK] | — |
| End-of-Life Status | Obsolete; replaced by Altera/Intel EPCQ family | — |
| Tipo de memoria | — | Flash (Enhanced Configuration Device) |
| Tensión de alimentación | — | 3.3 V |
| Configuration Modes | — | Passive Parallel Synchronous (PPS), Passive Parallel Asynchronous (PPA), Passive Serial (PS) |
| Maximum Configuration Clock | — | 40 MHz |
| Number of Configuration Pages | — | Up to 8 (selectable via PGM[2..0]) |
| In-System Programmable | — | Yes (via JTAG / IEEE 1149.1) |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan and programming) |
| Supported FPGA Families | — | Altera Stratix, Cyclone, Arria series |
| Data Compression | — | Supported (15-30% density gain depending on target FPGA) |
| Temperatura de funcionamiento | — | -40C to +85C (industrial) |
| Lead-Free / RoHS | — | Lead-free (per JEDEC J-STD-020); RoHS compliance: [DATA_NEEDED] |
| Dynamic Reconfiguration | — | Yes (page mode via PGM[2..0] pins) |
| Configuration Controller | — | Integrated |