EPC1LC20 vs EPC1LC20-W Comparación
Comparación detallada lado a lado de EPC1LC20 por Intel y EPC1LC20-W por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC1LC20 | EPC1LC20-W |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,95 | $9,85 |
| Tipo de memoria | Non-volatile configuration memory (Flash/EPROM) | OTP (One-Time Programmable) Configuration PROM |
| Memory Capacity | 1 Mbit (1,048,576 bits) | — |
| Tipo de interfaz | Serial configuration interface | — |
| Maximum DCLK Frequency | 8 MHz | — |
| Tensión de alimentación | 3.3 V or 5.0 V | 3.3 V and 5.0 V |
| In-System Programmability | Yes (IEEE 1149.1 / JTAG) | — |
| Programmable Voltage | 5.0 V and 3.3 V ISP | — |
| Configuration Mode | Serial, multi-device daisy-chain capable | — |
| Encapsulado | 20-pin PLCC (J-leaded, surface mount) | 20-PLCC J-lead (9x9 mm) |
| Recuento de pines | 20 | — |
| Tipo de montaje | Surface Mount | Surface Mount (PLCC socket or direct solder) |
| Temperatura de funcionamiento | [DATA_NEEDED: Operating temperature range] | — |
| Compatible FPGA Families | ACEX 1K, APEX 20K, FLEX 10K, Cyclone, Mercury | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Compliant (Pb-free -W finish) |
| JTAG Pins | TCK, TMS, TDI, TDO | — |
| Tamaño de memoria | — | 1 Mbit |
| Configuration Clock (DCLK) | — | 8 MHz maximum |
| Interfaz | — | Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS) |
| In-System Programming | — | Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V |
| Lead Finish | — | Pb-free (matte tin) - "-W" suffix |
| Daisy-Chain Support | — | Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs |
| Compression Support | — | Yes - stores compressed Altera FPGA bitstreams |
| Rango de temperatura de funcionamiento | — | [DATA_NEEDED: operating temperature range] |
| Programming Cycles | — | 1 (OTP) |
| Target FPGA Families | — | Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury |