EPC1LC20HEC vs EPC2LC20 Comparación
Comparación detallada lado a lado de EPC1LC20HEC por Intel y EPC2LC20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC1LC20HEC | EPC2LC20 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,60 | $7,20 |
| Tipo de memoria | OTP Configuration PROM (EEPROM-based) | Non-volatile configuration PROM |
| Memory Density | 1 Mbit (1,048,576 bits) | — |
| Interfaz | Serial (4-wire: nCS, DCLK, DATA, nINIT_CONF) | — |
| Max Configuration Clock | 8 MHz | — |
| Tensión de alimentación | 3.3 V or 5 V | — |
| Programmability | One-Time Programmable (OTP) | — |
| Encapsulado | 20-pin PLCC (J-lead, 9x9 mm) | 20-pin PLCC (J-lead, 9x9 mm) |
| Temperatura de funcionamiento | 0C to +70C (commercial) | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| Daisy Chain Support | Yes | — |
| nINIT_CONF Pin | Yes (programmable as nCONFIG or nSTATUS) | — |
| DONE Pin | Yes | — |
| Compatible FPGA Families | APEX, ACEX, FLEX, Cyclone (legacy) | — |
| Tipo de montaje | Surface Mount (PLCC socket recommended) | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Non-Compliant (original Altera Pb-containing part) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Tamaño de memoria | — | 1.6 Mbit |
| Configuration Interface | — | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Programming Interface | — | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | — | 5.0 V or 3.3 V |
| Supported FPGA Families | — | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Cascade Support | — | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Lead-Free Version | — | EPC2LC20N available as lead-free equivalent |
| Programming Support | — | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | — | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |