EPC2LC20 - 1.6Mb In-System Prog Config PROM 20-PLCC | Altera
N.º de pieza: EPC2LC20 ✗ Fin de vida| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $14.5 | $14,50 |
| 10 | $12.85 | $128,50 |
| 100 | $10.4 | $1.040,00 |
| 500 | $8.75 | $4.375,00 |
| 1.000 | $7.2 | $7.200,00 |
EPC2LC20 Descripción general
A configuration PROM is a non-volatile memory device that stores the FPGA's configuration bitstream and delivers it serially or in parallel to the target SRAM-based FPGA every time the system powers up or when new configuration data is needed. Because SRAM-based LUT devices are volatile, the EPC2LC20 eliminates the need for a separate boot ROM and reduces BOM cost, PCB area, and design complexity. The EPC2 family sits in the broader hierarchy of FPGA configuration memory: configuration PROM -> non-volatile boot memory -> FPGA companion IC -> programmable logic support silicon.
Key features of the EPC2LC20 include 1.6 Mbits of storage capacity, cascadable JTAG-chain support so multiple EPC2 devices can be chained together to configure larger FPGAs, and dedicated open-drain CONF_DONE and nSTATUS pins for handshaking with the target FPGA. The device supports 8-bit or 16-bit JTAG boundary-scan, plus built-in data decompression compatible with Altera Quartus II programming files. Programming is performed via the Altera Programming Unit (APU) or any IEEE 1149.1-compliant JTAG controller.
In terms of architecture, the EPC2LC20 is built around a CMOS non-volatile memory array with on-chip charge pumps for ISP operation. It exposes standard JTAG pins (TCK, TMS, TDI, TDO) plus dedicated nCONFIG, nSTATUS, CONF_DONE and DCLK interface pins to the FPGA, so no glue logic is required between the PROM and the FPGA. The JTAG-based ISP allows field upgrades and factory-floor programming using only a 4-wire JTAG cable.
Typical applications include boot configuration for Cyclone and Cyclone II FPGA designs, APEX 20K family prototyping cards, multi-FPGA systems that daisy-chain several EPC2 devices in JTAG order, industrial controllers using FLEX 10K/6000 logic, and legacy designs that require a simple non-volatile companion to Altera SRAM-based FPGAs. When selecting between EPC2 variants, choose the EPC2LC20 for low-density designs and cascade additional EPC2s for larger FPGA bitstreams.
Alternativas directas para EPC2LC20 — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con EPC2LC20 (mismo factor de forma y huella) — difiere en Memory Type, Mounting Type, Package, Compatible FPGA Families, Interface.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
EPC2LC20N
✓ En stock
$7.4 / unidad
Ver hoja de datos →EPC2LI20
✓ En stock
$5.95 / unidad
Ver hoja de datos →EPC2LI20N
✓ En stock
$5.1 / unidad
Ver hoja de datos →EPC2LC120
✓ En stock
$9.95 / unidad
Ver hoja de datos →EPC1LC20
✓ En stock
$7.95 / unidad
Ver hoja de datos →EPC2LC20 Valores máximos y características eléctricas
| Tipo de memoria | Non-volatile configuration PROM |
| Tamaño de memoria | 1.6 Mbit |
| Configuration Interface | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Programming Interface | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Supply Voltage VCC | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | 5.0 V or 3.3 V |
| Supported FPGA Families | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Cascade Support | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Encapsulado | 20-pin PLCC (J-lead, 9x9 mm) |
| Tipo de montaje | Surface Mount |
| Estado RoHS | Non-Compliant (original Altera Pb-containing part) |
| Lead-Free Version | EPC2LC20N available as lead-free equivalent |
| Programming Support | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |
Configuración de pines de EPC2LC20
| Pin 1 | TCK — JTAG Test Clock |
| Pin 2 | TMS — JTAG Test Mode Select |
| Pin 3 | nCONFIG — Configuration control (from FPGA, input to PROM) |
| Pin 4 | nSTATUS — Configuration status (open-drain, to FPGA) |
| Pin 5 | DCLK — Configuration clock (to FPGA) |
| Pin 6 | DATA — Configuration data serial output to FPGA |
| Pin 7 | nCS — Chip select (cascade use) |
| Pin 8 | nCE — Chip enable (cascade use) |
| Pin 9 | VCC — Power supply (+3.3 V) |
| Pin 10 | VCC — Power supply (+3.3 V) |
| Pin 11 | GND — Ground |
| Pin 12 | GND — Ground |
| Pin 13 | OE — Output enable |
| Pin 14 | nRESET — Reset input |
| Pin 15 | TDI — JTAG Test Data In |
| Pin 16 | TDO — JTAG Test Data Out |
| Pin 17 | A0 — Address input / cascade select |
| Pin 18 | A1 — Address input / cascade select |
| Pin 19 | A2 — Address input / cascade select |
| Pin 20 | CONF_DONE — Configuration done flag (open-drain, to FPGA) |
Aplicaciones típicas
EPC2LC20 es adecuado para 6 aplicacións: Cyclone / Cyclone II FPGA Boot Configuration, APEX 20K Family Configuration, Multi-FPGA JTAG Daisy-Chain Systems, Industrial Controller FLEX 10K / FLEX 6000 Designs, Prototype & Development Boards, Legacy MAX 9000 / ACEX 1K Designs.
Cyclone / Cyclone II FPGA Boot Configuration
The EPC2LC20's 1.6-Mbit density and JTAG ISP interface align with Cyclone and Cyclone II configuration bitstreams up to ~200 Kbytes (compressed). It connects directly to the FPGA's nCONFIG/nSTATUS/CONF_DONE/DCLK pins, eliminating an external boot ROM and reducing BOM cost and PCB area. The 3.3-V VCC matches Cyclone's VCCIO domain, and the dedicated JTAG TAP enables field firmware updates without removing the board. For designs that exceed 1.6 Mb the EPC2LC120 in the same PLCC-20 footprint provides a higher-density upgrade path.
Recomendado
APEX 20K Family Configuration
The EPC2LC20 supports Altera's APEX 20K, APEX 20KC, and APEX 20KE multi-million-gate FPGAs in serial configuration mode. With 1.6 Mb of storage it fits smaller APEX 20K bitstreams; larger APEX designs cascade multiple EPC2 devices via JTAG. The PLCC-20 footprint is the same as APEX 20K EDA board designs, allowing drop-in placement in industrial automation and telecom hardware that still uses APEX 20K logic. The dedicated open-drain nSTATUS/CONF_DONE handshaking matches APEX 20K's PS mode timing.
Recomendado
Multi-FPGA JTAG Daisy-Chain Systems
When a single EPC2LC20 is insufficient, multiple EPC2 devices can be cascaded via JTAG to deliver larger configuration bitstreams to high-density FPGAs such as APEX II and Arria GX. The EPC2LC20 acts as one node in the JTAG chain, sharing TCK/TMS/TDI and passing TDO. The daisy-chain topology is supported natively in Quartus II programmer, so engineers do not need external mux logic. Industrial-grade parts (EPC2LI20N) are preferred in 24V factory-floor systems with elevated ambient temperature.
Recomendado
Industrial Controller FLEX 10K / FLEX 6000 Designs
Legacy industrial controllers built on Altera FLEX 10K and FLEX 6000 series logic continue to use EPC2LC20 as their boot configuration PROM. The 1.6-Mbit density is more than adequate for these older FPGA families, and the PLCC-20 socket allows easy field replacement. Designers maintaining FLEX-based equipment can substitute the EPC2LC20N (Pb-free) or EPC2LI20N (industrial Pb-free) as drop-in replacements. The JTAG ISP allows in-system firmware upgrades without opening the enclosure.
Recomendado
Prototype & Development Boards
Altera / Intel FPGA development kits for Cyclone, Cyclone II, APEX 20K, and ACEX 1K frequently reference EPC2LC20 as the on-board configuration PROM because it supports every supported FPGA family in a single package. The 20-pin PLCC socket simplifies rework during board bring-up. JTAG ISP via the APU or Quartus Programmer means designers can iterate bitstreams in-circuit. For RoHS-compliant builds the EPC2LC20N retains the same PLCC-20 footprint.
Recomendado
Legacy MAX 9000 / ACEX 1K Designs
Older MAX 9000 CPLDs and ACEX 1K FPGAs rely on EPC2LC20 for non-volatile boot. The 1.6 Mb of storage far exceeds ACEX 1K's typical 100 Kbit bitstream, leaving margin for design growth. The PLCC-20 pinout is identical to EPC2LI20 and EPC2LC20N, so existing boards can accept the lead-free conversion part with zero PCB rework. Maintenance and spare-parts inventories continue to stock EPC2LC20 because of its long service history in telecom and industrial automation.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para EPC2LC20 — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | EPC2LC20N | EPC2LI20 | EPC2LI20N | EPC2LC120 | EPC1LC20 |
|---|---|---|---|---|---|---|
| Package | 20-pin PLCC (9x9 mm) | 20-pin PLCC (9x9 mm) - same | 20-pin PLCC (9x9 mm) - same | 20-pin PLCC (9x9 mm) - same | 20-pin PLCC (9x9 mm) - same | 20-pin PLCC (9x9 mm) - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Memory Density | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 4 Mbit (larger) | 1 Mbit (smaller) |
| Programming Interface | IEEE 1149.1 JTAG ISP (5V/3.3V) | IEEE 1149.1 JTAG ISP | IEEE 1149.1 JTAG ISP | IEEE 1149.1 JTAG ISP | IEEE 1149.1 JTAG ISP | IEEE 1149.1 JTAG ISP |
| Cascade Support | Yes (JTAG chain) | Yes | Yes | Yes | Yes | Yes |
| Supported FPGA Families | ACEX 1K, APEX 20K, Cyclone, Cyclone II, FLEX 10K/6000, MAX 9000 | Same families | Same families | Same families | Same + larger bitstreams | Same families (smaller designs) |
Diferenciadores clave
- Direct Altera-original configuration PROM with native JTAG ISP (frente a Generic third-party SPI flash + soft-controller solutions)
- Pin-compatible Pb-free upgrade path (frente a EPC2LC20 (this part))
- 1.6 Mbit density matches the most common Cyclone II bitstreams (frente a EPC1LC20 (1 Mbit))
Notas de diseño
Place the EPC2LC20 within 50 mm of the target FPGA to keep the DCLK and DATA traces short and matched; long traces degrade signal integrity at higher DCLK rates. Provide a solid ground plane under the device and route JTAG signals (TCK, TMS, TDI, TDO) away from switching power and clock lines. Keep VCC and GND pin pairs (9/10 and 11/12) on a low-impedance 3.3-V plane.
The EPC2LC20 requires a stable 3.3-V supply; add a 0.1 uF ceramic decoupling capacitor close to each VCC pin (9 and 10) and a 10 uF bulk capacitor near the device. The 5.0-V ISP mode is supported on VCC at 3.3 V; do not exceed the absolute maximum VCC rating. If the host JTAG programmer drives 5-V logic on TDI/TMS, ensure the FPGA's JTAG VCCIO matches.
Do not confuse the EPC2LC20 (lead-containing) with the EPC2LC20N (Pb-free RoHS) when ordering for RoHS-compliant builds. In daisy-chained configurations, ensure nCS/nCE cascade logic is correct; a single mis-wired nCS line will prevent all downstream FPGAs from configuring. Confirmed FPGA nCONFIG must be held low at power-up before the EPC2LC20 releases CONF_DONE, otherwise the FPGA may start up in an undefined state.
Información de cumplimiento
EPC2LC20 is the original lead-containing Altera part; EPC2LC20N is the Pb-free / RoHS-compliant conversion variant in the same PLCC-20 footprint. AEC-Q100 is not applicable because this is a memory/configuration device, not an automotive-grade IC.
