EPC20LI20N vs EPC2LI20N Comparación
Comparación detallada lado a lado de EPC20LI20N por Intel y EPC2LI20N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC20LI20N | EPC2LI20N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | Memory ICs |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $17,50 | $5,10 |
| Tipo de memoria | EPROM (UV-erasable, in-system programmable) | Non-volatile configuration PROM (Flash) |
| Tamaño de memoria | 1.6 Mbit (65,536 x 1-bit words, approx. 200 Kbyte) | 1.6 Mbit |
| Interfaz | Serial (4-pin Altera Passive Serial: DCLK, DATA0, nCONFIG, nSTATUS) | — |
| Tensión de alimentación | 3.3 V (5.0 V compatible variant in same family) | — |
| Configuration Clock | Up to 10 MHz | — |
| Target FPGA Families | APEX II, APEX 20K/KC/KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA | — |
| Encapsulado | 20-pin PLCC (9x9 mm, JEDEC MS-018) | — |
| Tipo de montaje | Surface Mount (PLCC socket or direct solder) | Surface Mount |
| Programming Interface | IEEE 1532 / JTAG (in-system) | — |
| Temperatura de funcionamiento | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Standby Current | [DATA_NEEDED: standby current uA] | — |
| Active Configuration Current | [DATA_NEEDED: ICC active mA] | — |
| Programming Voltage | [DATA_NEEDED: VPP] | — |
| Programming Cycles | [DATA_NEEDED: endurance cycles] | — |
| Nivel MSL | [DATA_NEEDED: MSL rating] | — |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Multi-Device Daisy-Chain | Supported via nCASC pin | — |
| Programmable Type | — | In System Programmable (ISP via JTAG) |
| Configuration Mode | — | Serial |
| Maximum Configuration Frequency | — | 10 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| Supply Voltage (VCCIO) | — | 4.5 V to 5.5 V |
| Encapsulado / Carcasa | — | 20-PLCC (J-Lead), 9x9 mm |
| Packaging | — | Tube |
| Supported FPGA Series | — | ACEX 1K, APEX II, Cyclone, Stratix II |
| JTAG Interface | — | IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO) |
| Configuration Pins | — | nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE |
| Estado RoHS | — | [DATA_NEEDED: RoHS status] |