EPC21C20U vs EPC1LI20 Comparación
Comparación detallada lado a lado de EPC21C20U por Intel y EPC1LI20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC21C20U | EPC1LI20 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | Activo | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,85 | $8,50 |
| Manufacturer | Intel / Altera | — |
| Product Type | Configuration Device (Boot Flash) | — |
| Tamaño de memoria | 20 Mbit (2.5 Mbyte) | 1 Mb (1,048,576 bits) |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (3.3 V typical) | 5.0 V (4.75 V to 5.25 V) |
| Interfaz | Altera/Intel Passive Serial (PS) and Active Serial (AS), JTAG (IEEE 1149.1) | — |
| Encapsulado | 20-pin UBGA (Ultra FineLine BGA) - also called 20-pin FBGA | 20-pin PLCC (J-lead, 9x9 mm) |
| In-System Programmability | Yes (via JTAG) | — |
| Bitstream Compression Support | Yes | — |
| Cascade (Multi-Device) Support | Yes (nCASC daisy-chain) | — |
| Supported FPGA Families | APEX II, APEX 20KE, APEX 20KC, Mercury, Stratix, Cyclone, ACEX 1K, FLEX 10KE | — |
| Temperatura de funcionamiento | -40 C to +85 C (industrial) | [DATA_NEEDED: operating temperature range] |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount (PLCC socket compatible) |
| Estado RoHS | Compliant (per Intel/Altera product page) | [DATA_NEEDED: RoHS status - original Altera part may be non-RoHS SnPb finish] |
| Lead-Free | Yes | — |
| Configuration Mode | Passive Serial (PS) / Active Serial (AS) via FPGA controller | — |
| Tipo de memoria | — | OTP Configuration PROM (EPROM-based) |
| Configuration Interface | — | Altera Passive Serial / Altera Active Serial / JTAG (IEEE 1149.1) |
| Maximum Configuration Clock | — | 8 MHz |
| Programming Voltage (VPP) | — | 12.75 V (typical, factory-programmed via JTAG) |
| Recuento de pines | — | 20 |
| Cascading Support | — | Yes (nCASC pin for multi-device daisy chain) |
| Endurance | — | OTP (one-time programmable, 1000 erase-equivalent UV cycles for pre-program erase) |
| JTAG Programming | — | Yes (in-system via IEEE 1149.1) |
| Compatible FPGA Families | — | FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury |
| Nivel MSL | — | 1 (per Partstack datasheet record) |