EPC2L1696-10F vs EPC2L20U-HAF480119C Comparación
Comparación detallada lado a lado de EPC2L1696-10F por Altera y EPC2L20U-HAF480119C por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPC2L20U-HAF480119C - FPGA Config Device, SRAM LUT | Intel
EPC2L20U-HAF480119C ⚠ Última compraComparación de especificaciones
| Parámetro | EPC2L1696-10F | EPC2L20U-HAF480119C |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | NRND | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $10,75 |
| Device Type | Configuration EPROM for SRAM-based LUT FPGAs | — |
| Supported Logic Density | 1696 LUTs | — |
| Configuration Interface | 5-pin Altera serial (nCS, DCLK, DATA, OE, nINIT_CONF) | — |
| Memory Technology | CMOS EEPROM | — |
| Supply Voltage (VCC) | 3.3 V | — |
| Access Time | 10 ns (speed grade -10) | — |
| Maximum DCLK Frequency | [DATA_NEEDED: DCLK max frequency] | — |
| Program / Erase Cycles | >= 100,000 cycles | — |
| Data Retention | [DATA_NEEDED: data retention years] | — |
| In-System Programming | Yes (4-wire JTAG-style interface) | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | — |
| Encapsulado | 20-pin PLCC | PLCC-20 |
| Tipo de montaje | Surface Mount | Surface Mount / Socketed |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Tipo de memoria | — | Configuration PROM (non-volatile) |
| Tamaño de memoria | — | 1.6 Mb |
| Target Device | — | SRAM-based LUT FPGAs (Cyclone, Stratix, APEX families) |
| Core Supply Voltage | — | 3.3 V |
| I/O Tolerance | — | 5 V tolerant |
| Configuration Modes | — | Serial (1-bit), Parallel (8-bit FPP), JTAG |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Programmability | — | In-system programmable via JTAG |
| Cascade Support | — | Yes (multi-PROM chains for larger FPGAs) |
| Configuration Clock Range | — | 10 MHz to 40 MHz |
| Bitstream Compression Support | — | Yes (Cyclone/Stratix compressed bitstreams) |
| Rango de temperatura de funcionamiento | — | [DATA_NEEDED: operating temperature range] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |