EPC2L1696-10F vs EPC2L20U-HAF480119C Comparaison
Comparaison détaillée côte à côte de EPC2L1696-10F par Altera et EPC2L20U-HAF480119C par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EPC2L20U-HAF480119C - FPGA Config Device, SRAM LUT | Intel
EPC2L20U-HAF480119C ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPC2L1696-10F | EPC2L20U-HAF480119C |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | NRND | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $10,75 |
| Device Type | Configuration EPROM for SRAM-based LUT FPGAs | — |
| Supported Logic Density | 1696 LUTs | — |
| Configuration Interface | 5-pin Altera serial (nCS, DCLK, DATA, OE, nINIT_CONF) | — |
| Memory Technology | CMOS EEPROM | — |
| Supply Voltage (VCC) | 3.3 V | — |
| Access Time | 10 ns (speed grade -10) | — |
| Maximum DCLK Frequency | [DATA_NEEDED: DCLK max frequency] | — |
| Program / Erase Cycles | >= 100,000 cycles | — |
| Data Retention | [DATA_NEEDED: data retention years] | — |
| In-System Programming | Yes (4-wire JTAG-style interface) | — |
| Température de fonctionnement | 0C to +70C (commercial) | — |
| Boîtier | 20-pin PLCC | PLCC-20 |
| Type de montage | Surface Mount | Surface Mount / Socketed |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Type de mémoire | — | Configuration PROM (non-volatile) |
| Taille de mémoire | — | 1.6 Mb |
| Target Device | — | SRAM-based LUT FPGAs (Cyclone, Stratix, APEX families) |
| Core Supply Voltage | — | 3.3 V |
| I/O Tolerance | — | 5 V tolerant |
| Configuration Modes | — | Serial (1-bit), Parallel (8-bit FPP), JTAG |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Programmability | — | In-system programmable via JTAG |
| Cascade Support | — | Yes (multi-PROM chains for larger FPGAs) |
| Configuration Clock Range | — | 10 MHz to 40 MHz |
| Bitstream Compression Support | — | Yes (Cyclone/Stratix compressed bitstreams) |
| Plage de température de fonctionnement | — | [DATA_NEEDED: operating temperature range] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |