EPC2L20N vs EPC2L120N Comparación
Comparación detallada lado a lado de EPC2L20N por Altera y EPC2L120N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC2L20N | EPC2L120N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | Memory ICs | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $17,20 | $7,85 |
| Función | In-System Programmable Configuration PROM for SRAM-based LUT FPGAs | — |
| Tamaño de memoria | 1.6 Mbit | — |
| Programmable Type | In System Programmable (ISP) | — |
| Supply Voltage - VCCINT/VCCIO | 3.0 V to 3.6 V or 4.5 V to 5.5 V | — |
| Encapsulado / Carcasa | 20-LCC (J-Lead), PLCC-20 | — |
| Packaging | Tube | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | [DATA_NEEDED: industrial temp range] |
| Supported FPGA Families | Altera APEX, ACEX, Cyclone, FLEX 10K, Mercury (per datasheet) | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix |
| Configuration Interface | Serial (Altera FPP / PS configuration scheme) | — |
| Cascade Support | Yes (multi-PROM chain via CE control) | — |
| Programming Method | In-system via 4-wire ISP / JTAG-style | — |
| Tipo de montaje | Surface Mount (J-Lead PLCC) | — |
| Recuento de pines | 20 | — |
| Lead Finish | Matte Tin (Pb-free) | — |
| Nivel MSL | 3 (168 hours) | — |
| Estado RoHS | Compliant | unknown |
| Device Type | — | Configuration Device for SRAM-based LUT FPGAs |
| Manufacturer | — | Intel (formerly Altera) |
| Family | — | EPC2 (Enhanced Configuration Device) |
| Memory Capacity | — | 165,888 bits (400,000 gates equivalent) |
| Operating Voltage (VCCIO) | — | 2.7 V to 3.6 V |
| 5V Tolerance | — | Yes (5V-tolerant I/O) |
| Configuration Clock (FPP) | — | Up to 66 MHz |
| Configuration Clock (PS) | — | Up to 33 MHz |
| Internal Oscillator | — | 8 MHz with programmable divider |
| JTAG Interface | — | IEEE Std 1149.1 compliant, ISP support |
| Programming Cycles | — | 100,000 erase/program cycles |
| Sector Erase Time | — | [DATA_NEEDED: typical sector erase time] |
| Encapsulado | — | 84-pin PLCC (J-Lead) |
| Configuration Schemes | — | FPP, PS, JTAG, daisy chain |