EPC2L20N vs EPC2L120N Comparaison
Comparaison détaillée côte à côte de EPC2L20N par Altera et EPC2L120N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC2L20N | EPC2L120N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | Memory ICs | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $17,20 | $7,85 |
| Fonction | In-System Programmable Configuration PROM for SRAM-based LUT FPGAs | — |
| Taille de mémoire | 1.6 Mbit | — |
| Programmable Type | In System Programmable (ISP) | — |
| Supply Voltage - VCCINT/VCCIO | 3.0 V to 3.6 V or 4.5 V to 5.5 V | — |
| Boîtier / Format | 20-LCC (J-Lead), PLCC-20 | — |
| Packaging | Tube | — |
| Température de fonctionnement | 0C to +70C (commercial) | [DATA_NEEDED: industrial temp range] |
| Supported FPGA Families | Altera APEX, ACEX, Cyclone, FLEX 10K, Mercury (per datasheet) | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix |
| Configuration Interface | Serial (Altera FPP / PS configuration scheme) | — |
| Cascade Support | Yes (multi-PROM chain via CE control) | — |
| Programming Method | In-system via 4-wire ISP / JTAG-style | — |
| Type de montage | Surface Mount (J-Lead PLCC) | — |
| Nombre de broches | 20 | — |
| Lead Finish | Matte Tin (Pb-free) | — |
| Niveau MSL | 3 (168 hours) | — |
| Statut RoHS | Compliant | unknown |
| Device Type | — | Configuration Device for SRAM-based LUT FPGAs |
| Manufacturer | — | Intel (formerly Altera) |
| Family | — | EPC2 (Enhanced Configuration Device) |
| Memory Capacity | — | 165,888 bits (400,000 gates equivalent) |
| Operating Voltage (VCCIO) | — | 2.7 V to 3.6 V |
| 5V Tolerance | — | Yes (5V-tolerant I/O) |
| Configuration Clock (FPP) | — | Up to 66 MHz |
| Configuration Clock (PS) | — | Up to 33 MHz |
| Internal Oscillator | — | 8 MHz with programmable divider |
| JTAG Interface | — | IEEE Std 1149.1 compliant, ISP support |
| Programming Cycles | — | 100,000 erase/program cycles |
| Sector Erase Time | — | [DATA_NEEDED: typical sector erase time] |
| Boîtier | — | 84-pin PLCC (J-Lead) |
| Configuration Schemes | — | FPP, PS, JTAG, daisy chain |