EPC2L20U-HAF480119C vs EPC2L120 Comparación
Comparación detallada lado a lado de EPC2L20U-HAF480119C por Intel y EPC2L120 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPC2L20U-HAF480119C - FPGA Config Device, SRAM LUT | Intel
EPC2L20U-HAF480119C ⚠ Última compraComparación de especificaciones
| Parámetro | EPC2L20U-HAF480119C | EPC2L120 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | Última compra | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,75 | $5,20 |
| Tipo de memoria | Configuration PROM (non-volatile) | Configuration PROM (Flash-based) |
| Tamaño de memoria | 1.6 Mb | — |
| Target Device | SRAM-based LUT FPGAs (Cyclone, Stratix, APEX families) | — |
| Core Supply Voltage | 3.3 V | — |
| I/O Tolerance | 5 V tolerant | — |
| Configuration Modes | Serial (1-bit), Parallel (8-bit FPP), JTAG | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| Programmability | In-system programmable via JTAG | — |
| Cascade Support | Yes (multi-PROM chains for larger FPGAs) | — |
| Configuration Clock Range | 10 MHz to 40 MHz | — |
| Bitstream Compression Support | Yes (Cyclone/Stratix compressed bitstreams) | — |
| Encapsulado | PLCC-20 | PLCC-20 |
| Tipo de montaje | Surface Mount / Socketed | Surface Mount |
| Rango de temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | unknown |
| Density | — | 120 Kbit |
| Configuration Interface | — | Serial, FPGA-targeted |
| Operating Voltage | — | 2.7 V to 3.6 V (3.3 V typ) |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Compatible FPGAs | — | Altera Cyclone, Cyclone II, APEX-series |
| Temperatura de funcionamiento | — | -40 C to +85 C |
| CONF_DONE Output | — | Open-drain, wire-OR capable |
| Data Retention | — | 20 years (per Altera datasheet family) |
| Program/Erase Cycles | — | 100 cycles minimum |
| Family | — | EPC2 (Enhanced Configuration) |