EPC2LC20NA vs EPC1LI20 Comparación
Comparación detallada lado a lado de EPC2LC20NA por Altera y EPC1LI20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC2LC20NA | EPC1LI20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $5,50 | $8,50 |
| Manufacturer | Altera Corporation (Intel Programmable Solutions Group) | — |
| Tipo de memoria | Configuration PROM (Flash-based, ISP) | OTP Configuration PROM (EPROM-based) |
| Memory Density | 1.6 Mbit | — |
| Operating Voltage (VCC) | 3.3 V | — |
| Interfaz | Serial (passive-serial) data output to FPGA | — |
| Programmability | In-system programmable via IEEE 1532 JTAG | — |
| Encapsulado | 20-pin PLCC (9x9 mm) | 20-pin PLCC (J-lead, 9x9 mm) |
| Tipo de montaje | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| Temperatura de funcionamiento | -40C to +85C (industrial grade) | [DATA_NEEDED: operating temperature range] |
| Supported FPGA Families | APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, Cyclone, Mercury | — |
| JTAG Compliance | IEEE Std 1149.1 / IEEE 1532 | — |
| Configuration Mode | Passive Serial (PS) | — |
| Estado RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status - original Altera part may be non-RoHS SnPb finish] |
| Daisy-Chain Support | Yes | — |
| Recommended Companion FPGA | Altera Cyclone, FLEX 10K, APEX 20K series | — |
| Tamaño de memoria | — | 1 Mb (1,048,576 bits) |
| Configuration Interface | — | Altera Passive Serial / Altera Active Serial / JTAG (IEEE 1149.1) |
| Maximum Configuration Clock | — | 8 MHz |
| Supply Voltage (VCC) | — | 5.0 V (4.75 V to 5.25 V) |
| Programming Voltage (VPP) | — | 12.75 V (typical, factory-programmed via JTAG) |
| Recuento de pines | — | 20 |
| Cascading Support | — | Yes (nCASC pin for multi-device daisy chain) |
| Endurance | — | OTP (one-time programmable, 1000 erase-equivalent UV cycles for pre-program erase) |
| JTAG Programming | — | Yes (in-system via IEEE 1149.1) |
| Compatible FPGA Families | — | FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury |
| Nivel MSL | — | 1 (per Partstack datasheet record) |